The reduction in memory cell and other circuit size required for high density static random access memories (SRAMs) and other circuitry is a continuing goal in semiconductor fabrication. SRAMs are used in applications where high-speed random access memories provide significant performance advantages over other types of random access memories, such as dynamic random access memories (DRAMs). However, because SRAMs draw greater electrical power per stored datum than DRAMs, and also because SRAM cells typically consume significantly more silicon real estate than DRAM cells, marked performance advantages are needed in order to justify the increased real estate and power budgets necessitated by inclusion of SRAMs. A typical application for SRAM is in what is known as a “cache” memory.
One or more cache memories are typically coupled to a central processing unit (CPU) or an arithmetic logic unit (ALU) in a processor module or chip in order to store recently-executed instructions and/or data of current interest. Due to the fact that many processing tasks involve repetitive calculations and thus require the processor to re-execute recently-executed instructions (on, for example, a sequence of data points), there is a high probability of locating a needed instruction in the cache memory and thus of providing that instruction more rapidly via the cache memory than is possible with other kinds of memories and/or memory management schemes. As a result, SRAMs can provide significant performance advantages, particularly in situations where large datasets are frequently manipulated.
One conventional SRAM architecture uses six transistors and is referenced as a 6T architecture. Another conventional SRAM architecture includes four transistors and two load devices, usually either resistors or PMOS active load devices. Either of these architectures results in a memory cell requiring significantly more area than a DRAM cell, but each provides significantly improved access time when compared to DRAM arrays.
One example of a more compact SRAM cell is described in “A 1:9 μm2 Loadless CMOS Four-Transistor SRAM Cell In A 0.18-μm Logic Technology”, by K Noda et al., presented at the 1998 International Electron Devices Meeting, 1998, pp. 643-6. The SRAM cell described therein achieves dimensions of 1.04 μm×1.86 μm, or about 60 F2, where F is related to a minimum lithographic feature size, as is described in more detail hereinbelow with reference to FIG. 2. While the area of this SRAM cell compares favorably to conventional SRAM cell areas (as described in Table 3 of the reference), the area of this SRAM cell is represented in the reference to be still at least three to six times that of conventional DRAM cells.
Accordingly, what is needed includes apparatus and methods for providing compact SRAM cells and memory cell arrays.